Silicon carbide inversion channel mosfets

ABSTRACT

Silicon carbide devices and methods of fabricating silicon carbide devices are provided by forming a first p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate. At least one first region of n-type silicon carbide is formed extending through the first p-type silicon carbide epitaxial layer and to the n-type silicon carbide substrate so as to provide at least one channel region in the first p-type silicon carbide epitaxial layer. At least one second region of n-type silicon carbide is also formed adjacent and spaced apart from the first region of n-type silicon carbide. A gate dielectric is formed-over the first region of n-type silicon carbide and at least a portion of the second region of n-type silicon carbide. A gate contact is formed on the gate dielectric. A first contact is also formed so as to contact a portion of the p-type epitaxial layer and the second region of n-type silicon carbide. A second contact is also formed on the substrate. Thus, a silicon carbide power device may be formed without the need for a p-type implant.

FIELD OF THE INVENTION

[0001] This invention relates to methods of fabricating power devices and the resulting devices, and more particularly to silicon carbide power devices and methods of fabricating silicon carbide power devices.

BACKGROUND OF THE INVENTION

[0002] Power devices are widely used to carry large currents and support high voltages. Modern power devices are generally fabricated from monocrystalline silicon semiconductor material. One widely used power device is the power Metal Oxide Semiconductor Field Effect Transistor (MOSFET). In a power MOSFET, a control signal is supplied to a gate electrode that is separated from the semiconductor surface by an intervening insulator, which may be, but is not limited to, silicon dioxide. Current conduction occurs via transport of majority carriers, without the presence of minority carrier injection that is used in bipolar transistor operation. Power MOSFETs can provide an excellent safe operating area, and can be paralleled in a unit cell structure.

[0003] As is well known to those having skill in the art, power MOSFETs may include a lateral structure or a vertical structure. In a lateral structure, the drain, gate and source terminals are on the same surface of a substrate. In contrast, in a vertical structure, the source and drain are on opposite surfaces of the substrate.

[0004] One widely used silicon power MOSFET is the double diffused MOSFET (DMOSFET) which is fabricated using a double-diffusion process. In these devices, a p-base region and an n+ source region are diffused through a common opening in a mask. The p-base region is driven in deeper than the n+ source. The difference in the lateral diffusion between the p-base and n+ source regions forms a surface channel region. An overview of power MOSFETs including DMOSFETs may be found in the textbook entitled “Power Semiconductor Devices” by B. J. Baliga, published by PWS Publishing Company, 1996, and specifically in Chapter 7, entitled “Power MOSFET”, the disclosure of which is hereby incorporated herein by reference.

[0005] Recent development efforts in power devices have also included investigation of the use of silicon carbide (SiC) devices for power devices. Silicon carbide has a wide bandgap, a lower dielectric constant, a high breakdown field strength, a high thermal conductivity, and a high saturation electron drift velocity compared to silicon. These characteristics may allow silicon carbide power devices to operate at higher temperatures, higher power levels and with lower specific on-resistance than conventional silicon-based power devices. A theoretical analysis of the superiority of silicon carbide devices over silicon devices is found in a publication by Bhatnagar et al. entitled “Comparison of 6H—SiC, 3C—SiC and Si for Power Devices”, IEEE Transactions on Electron Devices, Vol. 40, 1993, pp. 645-655. A power MOSFET fabricated in silicon carbide is described in U.S. Pat. No. 5,506,421 to Palmour entitled “Power MOSFET in Silicon Carbide” and assigned to the assignee of the present invention.

[0006] Notwithstanding these potential advantages, it may be difficult to fabricate power devices including power MOSFETs in silicon carbide. For example, as described above, the double-diffused MOSFET (DMOSFET) is generally fabricated in silicon using a double diffusion process wherein the p-base region is driven in deeper than the n+ source. Unfortunately, in silicon carbide, the diffusion coefficients of conventional p- and n-type dopants are small compared to silicon, so that it may be difficult to obtain the required depths of the p-base and n+ source regions using acceptable diffusion times and temperatures. Ion implantation may also be used to implant the p-base and the n+ source. See, for example, “High-Voltage Double-Implanted Power MOSFET's in 6H—SiC” by Shenoy et al., IEEE Electron Device Letters, Vol. 18, No. 3, March 1997, pp. 93-95. However, it may be difficult to control the depth and lateral extent of ion implanted regions. Moreover, the need to form a surface channel surrounding the source region may require the use of two separate implantation masks. It may then be difficult to align the p-base and the source regions to one another, thereby potentially impacting the device performance.

[0007] Methods of forming FETs in silicon carbide utilizing p-type implantation have also been described by, for example, commonly assigned U.S. patent application Ser. No. 09/093,207 entitled “Self-Aligned Method of Fabricating Silicon Carbide Power Devices by Implantation and Lateral Diffusion,” the disclosure of which is incorporated herein by reference as if set forth fully herein. Also, PCT International Publication No. WO98/02916 describes a method for producing a doped p-type channel region layer having on laterally opposite sides thereof doped n-type regions in a silicon carbide layer for producing a voltage-controlled semiconductor device. A masking layer is applied on top of a silicon carbide layer that is lightly n-doped. An aperture is etched in the masking layer extending to the silicon carbide layer. N-type dopants are implanted into an area of the silicon carbide layer defined by the aperture for obtaining a high doping concentration of n-type in the surface-near layer of the silicon carbide layer under the area. P-type dopants having a considerably higher diffusion rate in silicon carbide than the n-type dopants, are implanted into an area of the silicon carbide layer defined by the aperture to such a degree that the doping type of the surface-near layer is maintained. The silicon carbide layer is then heated at such a temperature that the p-type dopants implanted in the surface-near layer diffuse into the surrounding regions of the silicon carbide layer that is lightly n-doped, to such a degree that a channel region layer in which p-type dopants dominates is created laterally to the highly doped n-type surface-near layer and between this layer and lightly n-doped regions of the silicon carbide layer. As described in this International Application, the heating is carried out a temperature above 1650° C. and below 1800°.

[0008] As the above illustrates, the difficulties of implantation and diffusion in silicon carbide may make the production of power devices such as the DMOSFET. Accordingly, improvements may be needed in manufacturing processes and device structures of silicon carbide devices such as silicon carbide DMOSFETs.

SUMMARY OF THE INVENTION

[0009] In first embodiments, the present invention provides methods of fabricating silicon carbide devices by forming a first p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate. At least one first region of n-type silicon carbide is formed extending through the first p-type silicon carbide epitaxial layer and to the n-type silicon carbide substrate so as to provide at least one channel region in the first p-type silicon carbide epitaxial layer. At least one second region of n-type silicon carbide is also formed adjacent and spaced apart from the first region of n-type silicon carbide. A gate dielectric is formed over the first region of n-type silicon carbide and at least a portion of the second region of n-type silicon carbide. A gate contact is formed on the gate dielectric. A first contact is also formed so as to contact a portion of the p-type epitaxial layer and the second region of n-type silicon carbide. A second contact is also formed on the substrate. Thus, a silicon carbide power device may be formed without the need for a p-type implant.

[0010] In particular embodiments of the present invention, the formation of at least one first region of n-type silicon carbide through the first p-type silicon carbide epitaxial layer and to the n-type silicon carbide substrate so as to provide at least one channel region in the first p-type silicon carbide epitaxial layer and at least one second region of n-type silicon carbide which is adjacent and spaced apart from the first region of n-type silicon carbide is carried out by implanting n-type dopants in the p-type silicon carbide epitaxial layer. Furthermore, in an alternative embodiment of the present invention, the formation of at least one first region of n-type silicon carbide through the first p-type silicon carbide epitaxial layer and to the n-type silicon carbide substrate so as to provide at least one channel region in the first p-type silicon carbide epitaxial layer may be preceded by etching a trench in the first p-type silicon carbide epitaxial layer. In such an embodiment, the n-type dopants may be implanted in exposed surfaces of the trench.

[0011] Preferably, the implantation of n-type dopants in the p-type silicon carbide epitaxial layer is followed by the activation of the implanted n-type dopants. Such activation may be accomplished by exposing the implanted first p-type epitaxial layer to a temperature of from about 900° C. to about 1400° C. Preferably, the n-type dopant is phosphorous. In such a case, it may be preferred that the activation of the phosphorous be carried out at a temperature of about 1200° C. Such annealing temperatures may activate the implanted ions with less damage to the silicon carbide than higher temperatures.

[0012] In other embodiments of the present invention, exposed portions of the first p-type epitaxial layer are capped with a passivating material prior to activating the implanted n-type dopants. In a further embodiment, the gate dielectric may be formed by patterning the passivating material so as to provide the gate dielectric.

[0013] In still further embodiments of the present invention, a second p-type silicon carbide epitaxial layer is formed on the p-type silicon carbide epitaxial layer. The second p-type silicon carbide epitaxial layer preferably has a carrier concentration higher than the first p-type silicon carbide epitaxial layer. The second p-type silicon carbide epitaxial layer may then be patterned so as to provide a at least one p+ contact region, wherein the at least one p+ contact region is adjacent the at least one second n-type region and wherein the at least one second n-type region is between the at least one p+ contact region and the at least one first n-type region. In a further embodiment, the first contact is formed so as to contact the at least one p+ contact region and the at least one second region of n-type silicon carbide. Thus a high quality contact may be formed without requiring p-type implantation.

[0014] In yet other embodiments of the present invention, a voltage absorbing region is formed around the silicon carbide device. In particular embodiments, the voltage absorbing region is formed by etching the first p-type epitaxial layer so as to form at least one step having a sidewall which extends into the first p-type silicon carbide epitaxial layer and wherein the sidewall of the at least one step is spaced apart from the at least one second n-type region. In further embodiments the p-type epitaxial layer is etched to form a plurality of steps. Furthermore, n-type dopants may be implanted in the at least one step of the first p-type epitaxial layer to compensate p-type dopants in the first p-type epitaxial layer. Preferably, the n-type dopants are implanted at a distance from the sidewall of the step based on a desired breakdown voltage of the power device.

[0015] In particular embodiments of the present invention, the formation of the gate dielectric comprises forming an oxide layer over exposed portions of the first p-type epitaxial layer and the formation of the first contact comprises etching the oxide layer so as to form a first contact hole and depositing metal in the first contact hole.

[0016] In further embodiments of the present invention, a unit cell of a vertical silicon carbide power device includes a first p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate. At least one first region of n-type silicon carbide extends through the first p-type silicon carbide epitaxial layer to the n-type silicon carbide substrate so as to provide a channel region. At least one second region of n-type silicon carbide is adjacent and spaced apart from the first region of n-type silicon carbide. A gate dielectric extends over the first region of n-type silicon carbide and at least a portion of the second region of n-type silicon carbide. A gate contact is formed on the gate dielectric. A first contact contacts a portion of the p-type epitaxial layer and the second region of n-type silicon carbide and a second contact is formed on the substrate.

[0017] In further embodiments of the present invention, the first and second regions of n-type silicon carbide are regions of the first p-type epitaxial layer with implanted n-type dopants. In still further embodiments, a trench is formed in the first p-type epitaxial layer and wherein the channel region comprises a region of n-type silicon carbide adjacent sidewalls of the trench.

[0018] In still further embodiments, at least one p-type contact region of epitaxial p-type silicon carbide is formed on the first p-type epitaxial layer, wherein the at least one p-type contact region has a carrier concentration higher than the first p-type silicon carbide epitaxial layer so as to provide at least one p+ contact region. The at least one p+ contact region is adjacent the at least one second n-type region and the at least one second n-type region is between the at least one p+ contact region and the at least one first n-type region. In a further embodiment, the first contact contacts the at least one p+ contact region and the at least one second region of n-type silicon carbide.

[0019] In still other embodiments, the first p-type epitaxial layer is on an n-type epitaxial layer which is on the n-type substrate, wherein the n-type epitaxial layer has a carrier concentration which is less than that of the n-type substrate.

[0020] In other embodiments of the present invention, the first p-type epitaxial layer forms at least one step having a sidewall which extends into the first p-type silicon carbide epitaxial layer and wherein the sidewall of the at least one step is spaced apart from the at least one second n-type region. Furthermore, the first p-type epitaxial may also form a plurality of steps. A compensation region of n-type dopants may also be formed in the at least one step to compensate p-type dopants in the first p-type epitaxial layer. The compensation region may be a distance from the sidewall of the step corresponding to a desired breakdown voltage of the power device.

[0021] In still further embodiments of the present invention, a passivating layer is formed on exposed portions of the p+ contact regions and the first p-type epitaxial layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022]FIG. 1 is a cross-sectional view of embodiments of a power MOSFETs according to the present invention.

[0023]FIGS. 2 through 6 are cross-sectional views illustrating embodiments of methods according to the present invention for producing the power MOSFET of FIG. 1.

[0024]FIG. 7A is a cross-sectional view illustrating methods of fabricating silicon carbide power MOSFETS according to embodiments of the present invention.

[0025]FIG. 7B is a cross-sectional view illustrating methods of fabricating silicon carbide power MOSFETs according to alternative embodiments of the present invention.

[0026] FIGS. 8-11 are cross-sectional views of embodiments of methods of fabricating silicon carbide power MOSFETs according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0027] The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0028] Referring now to FIG. 1, embodiments of a vertical power MOSFET and unit cell of a vertical power MOSFET are illustrated. It will be understood by those having skill in the art that the vertical silicon carbide MOSFETs are generally replicated in a unit cell. Such unit cells are illustrated between lines 100 a and 100 c or lines 100 b and 100 c. For ease of illustration, a two unit cell MOSFET will be described, however, as will be appreciated by those of skill in the art, additional unit cells may be incorporated into a MOSFET along one direction or along two, generally orthogonal directions, while still benefiting from the teachings of the present invention.

[0029] As is seen in FIG. 1, a MOSFET according to embodiments of the present invention preferably includes an n⁺ monocrystalline silicon carbide substrate 10. An n⁻ silicon carbide layer 12 is provided on a first face of the substrate 10. A p-type epitaxially formed silicon carbide p-well region 14 is on the n-type layer 12. A contact region 18 of epitaxially formed p⁺ silicon carbide may also be provided. Adjacent the contact region 18 is an n⁺ source region 20 of silicon carbide which is provided in the p-type epitaxial region 14. Adjacent and spaced apart from the n⁺ source region 20 is an n-type silicon carbide channel region 21 which extends to the n⁻ layer 12. A gate insulating layer 22 of a suitable dielectric material, such as SiO₂, extends over the channel region 21 and to the n+ source regions 20. A gate contact 26 is provided on the gate layer opposite the channel region 21. Source contact 24 is provided between the p⁺ contact regions 18 and the n⁺ source regions 20 and drain contact 28 is provided on the face of the substrate 10 opposite the p-type epitaxial region 14.

[0030] Also illustrated in FIG. 1 is a voltage absorbing region which may distribute the electric field at the perimeter of the MOSFET so as to reduce field crowding. In particular, the voltage absorbing region may be formed by forming a step or steps in the p-type epitaxial region 14. Such a step may form a mesa having a sidewall 15 which surrounds the device. Furthermore, a p⁻ region 16 may be formed at the periphery of the device to further distribute the electric field. Formation of such a voltage absorbing region and alternative embodiments of such a voltage absorbing region are described in further detail below. However, the present invention should not be construed as limited to the particular voltage absorbing region configurations illustrated in the figures but may also include variations to such configurations. For example, multiple steps in the p-type epitaxial region 14 may be provided. Similarly, the p⁻ region 16 may be graded to further distribute the electric field.

[0031] Embodiments of the methods of fabrication according to the present invention will now be described. As seen in FIG. 2, an n⁻ epitaxial layer 12 is formed on an n⁺ silicon carbide substrate 10. The n layer 12 may have a thickness of from about 5 to about 200 μm and a doping to provide a carrier concentration of from about 1×10¹⁴ cm⁻³ to about 1×10¹⁷ cm⁻³. A p-type epitaxial layer 40 is then grown on the n⁻ epitaxial layer 12. The p-type epitaxial layer 40 may have a thickness of from about 0.5 to about 3 μm and a doping to provide a carrier concentration of from about 2×10¹⁶ cm⁻³ to about 5×10⁷ cm⁻³. If contact regions 18 are utilized, then a second, more highly doped, p⁺ epitaxial layer 42 may then be grown on the p-type epitaxial layer 14. The p⁺ epitaxial layer 42 may have a thickness of from about 0.1 to about 1 μm and a doping to provide a carrier concentration of from about 5×10¹⁸ cm⁻³ to about 1×10²¹ cm⁻³.

[0032] As seen in FIG. 3, the p⁺ epitaxial layer 42 is then patterned to form the contact regions 18. Such a patterning may be provided by selectively oxidizing or masking and etching the p⁺ epitaxial layer 42 utilizing techniques suitable for silicon carbide. Patterning techniques are known to those of skill in the art and, therefore, will not be described in detail herein. Alternatively, the contact regions 18 may be formed by masking and selective epitaxial deposition. Preferably, the contact regions 18 have a width of from about 0.1 μm to about 10 μm, however, any suitable width which may allow for good ohmic contact formation may be provided. As will be appreciated by those of skill in the art, if the optional contact regions 18 are not utilized, then the patterning operations illustrated in FIG. 3 may be omitted from the fabrication process.

[0033]FIGS. 4 and 5 illustrate the formation of a voltage absorbing region. As seen in FIG. 4, the p-type epitaxial layer 14 is etched so as to form a step in the p-type epitaxial layer 14. The voltage absorbing region may have one or more steps so as to gradually reduce the thickness of the p-type epitaxial layer 14. The thickness of the p-type epitaxial layer 14 is preferably reduced so that the product of the thickness and the doping of the carrier concentration of the p-type epitaxial layer 14 is between about 1×10¹² cm⁻². As is further seen in FIG. 5, the p⁻ silicon carbide regions 16 may be formed in the p-type epitaxial layer 16 through, for example, ion implantation techniques known to those of skill in the art. Such implantation may be accomplished by masking and then implanting n-type dopants to compensate a region of the p-type epitaxial layer 14 utilizing techniques known to those of skill in the art. Preferably, the distance between the contact regions 18 and the p⁻ regions 16 is based on the desired breakdown voltage of the device. For example, a distance of about 150 μm may be suitable for a 2 kV device. As will be appreciated by those of skill in the art, other distances may be utilized while benefiting from the teachings of the present invention.

[0034]FIG. 6 illustrates the formation of the source regions 20. As seen in FIG. 6, source regions 20 are formed by implanting n-type dopants into the p-type epitaxial layer 14 adjacent the p+ contact regions 18 if present. Otherwise, if the contact regions 18 are not utilized, the source regions 20 may be formed by implanting spaced apart regions in the p-type epitaxial layer 14. Preferably, the n-type dopant utilized for all n-type implants is phosphorous, however, nitrogen or other n-type dopants may also be utilized.

[0035]FIGS. 7A and 7B illustrate formation of the channel region 21 according to alternative embodiments of the present invention. As seen in FIG. 7A, the channel region 21 may be formed by masking and implanting n-type dopants in the p-type epitaxial layer 14 adjacent but spaced apart from the source regions 20 so as to form the channel region 21 which extends through the p-type epitaxial layer 14 to the n-type epitaxial layer 12. When the device is turned-on, this n-type channel region provides a path from the MOS channel to the lightly doped drift region, allowing electrons to flow from source regions to drain regions. In the off-state, this n-channel region may be depleted of electrons from the reverse biased pn junction, which is formed on both sides of the channel region. The pn-junctions on both sides of the channel region may shield the MOS region from high electric fields at off state, which may result in a higher device reliability compared to trench devices, such as UMOSFETs.

[0036] Any suitable n-type dopants may be utilized; however, phosphorous is preferred. The carrier concentration of the n-type channel 21 is preferably from 1 to 200% that of the p-type epitaxial layer 14 and more preferably from 30 to 50% (e.g. from about 1×10¹⁶ cm⁻³ to 2×10¹⁷ cm⁻³). As seen in FIG. 7B, in an alternative embodiment of the present invention, the channel region 21′ may also be formed by first etching a trench 50 in the p-type epitaxial layer 14 and then implanting n-type dopants in the exposed portions (the bottom and sidewalls) of the trench 50 so as to provide the channel region 211. Similar carrier concentrations are preferred for the alternative embodiment illustrated in FIG. 7B as for the embodiment illustrated in FIG. 7A.

[0037] The present invention will further be described with reference to FIGS. 8 through 11 which illustrate fabrication operations for the embodiment illustrated in FIG. 7A. As will be appreciated by those of skill in the art, these fabrication operations may be carried out on the embodiment of the present invention illustrated in FIG. 7B with corresponding changes to, for example, formation of the gate dielectric layer and gate contact so as to accommodate the different structure of the channel region 21′. Thus, operations according to the present invention are illustrated with reference to channel region 21 of FIG. 7A, and, corresponding operations performed for devices having the channel region 21′ illustrated in FIG. 7B need not be described in detail as such operations will be apparent to those of skill in the art in light of the present discussion.

[0038] As seen in FIG. 8, the voltage absorbing region may be etched to isolate the device. Such an etching process may etch through the p-type epitaxial layer 14 to the n-type epitaxial layer 12 so as to form a mesa having a sidewall which extends to and/or into the n-type epitaxial layer 12. Alternatively, the sidewall of the mesa could extend through the n-type epitaxial layer 12 and to and/or into the substrate 10. Preferably, the sidewall of the mesa extends through the p⁻ region 16 at a distance from the source contact region 18 based upon the desired breakdown voltage of the device as described above. Alternatively, the voltage absorbing region may be formed by masking and selective epitaxial growth of the epitaxial layer 40. In such an embodiment of the present invention, the formation of the structure of FIG. 2 would be modified to incorporate the selective epitaxial growth process.

[0039]FIG. 9 illustrates formation of an optional cap layer 52 of a deposited oxide and/or other passivating material. The cap layer 52 may have a thickness of from about 0.01 μm to about 1 μm. In any event, whether a cap layer 52 is utilized or not, the device is preferably exposed to a high temperature anneal ranging from about 900° C. to about 1500° C. and preferably less than about 1400° C. and more preferably less than about 1300° C. for several minutes so as to activate the n-type implants. For example, if nitrogen is utilized as the n-type dopant, then an anneal at about 1300° C. for about 3 hours may be utilized. If phosphorous is utilized as the n-type dopant, then an anneal at about 1200° C. for about 3 hours may be utilized.

[0040] As illustrated in FIG. 10, after the anneal, the cap layer 52 may be stripped off of the device and a layer 52′ of dielectric material deposited on the device so as to provide a gate dielectric material. Alternatively, the cap layer 52 may be used as the gate dielectric material. In either case, a gate contact 26 may be formed by forming a metal contact on the gate dielectric material. Suitable gate contact materials include, but not limited to, aluminum, polysilicon and molybdenum. Furthermore, as will be appreciated by those of skill in the art, a multi-layered gate contact may also be utilized.

[0041] As is illustrated in FIG. 11, contact holes may be formed in the dielectric material 52′ and ohmic contacts formed in the contact holes to provide source contacts 24. Similarly, an ohmic contact 28 may be formed on the substrate 10. Suitable ohmic contact materials include, but not limited to, nickel, titanium alloy, and aluminum. The deposited metal contacts may then be sintered at a high temperature ranging from about 500° C. to about 1200° C. An overlayer metal may also be deposited on the contacts, for example, to facilitate connection to the device.

[0042] It will be understood by those having skill in the art that the order of steps in FIGS. 1-7A and 7B-11 may be changed. Thus, for example, the channel region 21 or 21′ of FIG. 7A or 7B may be formed before forming the n⁺ regions 20 of FIG. 6. Similarly, the p⁻ regions 16 may be formed either before or after formation of the n⁺ regions 20 or channel region 21 or 21′. Similarly, the contacts 24 may be formed by, for example, depositing and patterning a metal layer, and then the dielectric layer 30 provided and openings in the dielectric layer formed to the contacts 18. Accordingly, the present invention should not be construed as limited to the exact sequence of operations described herein but is intended to encompass other sequences of fabrication which will become apparent to those of skill in the art in light of the present disclosure.

[0043] In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims. 

What is claimed is:
 1. A method of fabricating a silicon carbide power device comprising the steps of: forming a first p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate; forming at least one first region of n-type silicon carbide through the first p-type silicon carbide epitaxial layer and extending to the n-type silicon carbide substrate so as to provide at least one channel region in the first p-type silicon carbide epitaxial layer; forming at least one second region of n-type silicon carbide in the first p-type silicon carbide epitaxial layer which is adjacent and spaced apart from the first region of n-type silicon carbide; and forming a gate dielectric on the first region of n-type silicon carbide and at least a portion of the second region of n-type silicon carbide.
 2. A method according to claim 1, further comprising the steps of: forming a gate contact on the gate dielectric; forming a first contact so as to contact a portion of the p-type epitaxial layer and the second region of n-type silicon carbide; and forming a second contact on the substrate.
 3. A method according to claim 1, further comprising the step of forming a patterned second p-type silicon carbide epitaxial region on the p-type silicon carbide epitaxial layer so as to provide a at least one p+ contact region, wherein the at least one p+ contact region is adjacent the at least one second n-type region and wherein the at least one second n-type region is between the at least one p+ contact region and the at least one first n-type region.
 4. A method according to claim 3, wherein the step of forming a patterned second p-type silicon carbide epitaxial region comprises the steps of: forming a second p-type silicon carbide epitaxial layer on the p-type silicon carbide epitaxial layer, wherein the second p-type silicon carbide epitaxial layer has a carrier concentration higher than the first p-type silicon carbide epitaxial layer; patterning the second p-type silicon carbide epitaxial layer so as to provide a at least one p+ contact region, wherein the at least one p+ contact region is adjacent the at least one second n-type region and wherein the at least one second n-type region is between the at least one p+ contact region and the at least one first n-type region.
 5. A method according to claim 3, further comprising the steps of: forming a gate contact on the gate dielectric; forming a first contact so as to contact a portion of the p-type epitaxial layer and the second region of n-type silicon carbide; and forming a second contact on the substrate.
 6. A method according to claim 5, wherein the step of forming a first contact so as to contact a portion of the p-type epitaxial layer and the second region of n-type silicon carbide comprises the step of forming a first contact which contacts the at least one p+ contact region and the at least one second region of n-type silicon carbide.
 7. A method according to claim 3, wherein the steps of forming at least one first region of n-type silicon carbide through the first p-type silicon carbide epitaxial layer and extending to the n-type silicon carbide substrate so as to provide at least one channel region in the first p-type silicon carbide epitaxial layer and forming at least one second region of n-type silicon carbide which is adjacent and spaced apart from the first region of n-type silicon carbide are carried out by implanting n-type dopants in the p-type silicon carbide epitaxial layer.
 8. A method according to claim 3, wherein the step of forming at least one first region of n-type silicon carbide through the first p-type silicon carbide epitaxial layer and to the n-type silicon carbide substrate so as to provide at least one channel region in the first p-type silicon carbide epitaxial layer is preceded by the step of etching a trench in the first p-type silicon carbide epitaxial layer and wherein the step of implanting n-type dopants comprises the step of implanting n-type dopants in exposed surfaces of the trench.
 9. A method according to claim 7, wherein the steps of implanting n-type dopants in the p-type silicon carbide epitaxial layer is followed by the step of activating the implanted n-type dopants.
 10. A method according to claim 9, wherein the step of activating the implanted n-type dopants comprises exposing the implanted first p-type epitaxial layer to a temperature of from about 900° C. to about 1400° C.
 11. A method according to claim 9, where the n-type dopants are nitrogen and wherein the step of activating comprises exposing the first p-type epitaxial layer to a temperature of about 1200° C.
 12. A method according to claim 10, wherein the step of exposing the implanted first p-type epitaxial layer is preceded by the step of capping exposed portions of the first p-type epitaxial layer with a passivating material.
 13. A method according to claim 12, wherein the step of forming a gate dielectric comprises the step of patterning the passivating material so as to provide the gate dielectric.
 14. A method according to claim 1, further comprising the step of forming a voltage absorbing region around the silicon carbide device.
 15. A method according to claim 13, wherein the step of forming a voltage absorbing region comprises the step of etching the firs t p-type epitaxial layer so as to form at least one step having a sidewall which extends into the first p-type silicon carbide epitaxial layer and wherein the sidewall of the at least one step is spaced apart from the at least one second n-type region and is formed opposite the at least one first n-type region.
 16. A method according to claim 15, wherein the p-type epitaxial layer is etched to form a plurality of step s.
 17. A method according to claim 15, further comprising the step of implanting n-type dopants in the at least one step to compensate p-type dopants in the first p-type epitaxial layer.
 18. A method according to claim 17, wherein the n-type dopants are implanted at a distance from the sidewall of the step based on a desired breakdown voltage of the power device.
 19. A method according to claim 11, wherein the step of forming a gate dielectric over the first region of n-type silicon carbide and at least a portion of the second region of n-type silicon carbide comprises forming an oxide layer over exposed portions of the first p-type epitaxial layer and wherein the step of forming a first contact comprises the steps of etching the oxide layer so as to form a first contact hole and depositing metal in the first contact hole.
 20. A unit cell of a vertical silicon carbide power device, comprising: a first p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate; at least one first region of n-type silicon carbide which extends through the first p-type silicon carbide epitaxial layer to the n-type silicon carbide substrate; at least one second region of n-type silicon carbide which is adjacent and spaced apart from the first region of n-type silicon carbide; and a gate dielectric over the first region of n-type silicon carbide in the first p-type silicon carbide layer and at least a portion of the second region of n-type silicon carbide.
 21. A unit cell according to claim 20, further comprising: a gate contact on the gate dielectric; a first contact so as to contact a portion of the p-type epitaxial layer and the second region of n-type silicon carbide; and a second contact on the substrate.
 21. A unit cell according to claim 20, further comprising an n-type epitaxial layer between the first p-type silicon carbide epitaxial layer and the substrate.
 22. A unit cell according to claim 20, wherein the first and second regions of n-type silicon carbide are regions of the first p-type epitaxial layer with implanted n-type dopants.
 23. A unit cell according to claim 22, further comprising a trench in the first p-type epitaxial layer and wherein the channel region comprise a region of n-type silicon carbide adjacent sidewalls of the trench.
 24. A unit cell according to claim 21, further comprising: at least one p-type contact region of epitaxial p-type silicon carbide on the first p-type epitaxial layer, wherein the at least one p-type contact region has a carrier concentration higher than the first p-type silicon carbide epitaxial layer so as to provide a at least one p+ contact region, wherein the at least one p+ contact region is adjacent the at least one second n-type region and wherein the at least one second n-type region is between the at least one p+ contact region and the at least one first n-type region.
 25. A unit cell according to claim 24, wherein the first contact contacts the at least one p+ contact region and the at least one second region of n-type silicon carbide.
 26. A unit cell according to claim 25, wherein the first p-type epitaxial layer forms at least one step having a sidewall which extends into the first p-type silicon carbide epitaxial layer and wherein the sidewall of the at least one step is spaced apart from the at least one second n-type region and is formed opposite the at least one first n-type region.
 27. A unit cell according to claim 26, wherein the first p-type epitaxial forms a plurality of steps spaced apart from the at least one second n-type region and is formed opposite the at least one first n-type region.
 28. A unit cell according to claim 26, further a compensation region of n-type dopants in the at least one step to compensate p-type dopants in the first p-type epitaxial layer.
 29. A unit cell according to claim 28, wherein the compensation region is a distance from the sidewall of the step which corresponds to a desired breakdown voltage of the power device.
 30. A unit cell according to claim 28 further comprising a passivating layer formed on exposed portions of the p+ contact regions and the first p-type epitaxial layer. 